TUTORIAL 1

Ultra Low-Power ASIC Design for IoT SoC’s: A Digital Design Journey from Concept to a Chip

Abstract

Ultra low-power SoC’s are the heart of many IoT devices in present and future products. Many emerging wearable devices (medical or others) can be relaized only by mastering the design art of digital SoC’s.



This tutorial introduces the design steps and techniques needed to design ultra low-power IoT SoC’s using digital ASIC design flow.



The tutorial will introduce the the steps needed to carry on an IoT digital ASIC design from concept to a final tape-out ready GDSII. Necessary steps to perform simulation, Syntheis, place and route and chip finsihing will be explained. Static timing analysis, timing verfication and formal verfication will be covered.



Moreover, the tutorial will discuss ultra low power design techniques and it’s applications in the context of IoT ASICs.



Additionally, the tutorial will present the attendees with a sample digital design with all necessary scripts and to drive it through a tape-out proven flow from RTL to GDSII using Sysnopsys Tools.



The material covered will cover digital ASIC requirmenst for IoT, system level design, ultra-low power design techniques, RTL development and design verification tips, Synthesis, place, route, clock-tree, Static Timing Analysis, formal verfication methods and Chip finishing.



Motivation and Objectives

Importance to ICECS community:

IoT enables a very wide range of products that touches all aspect of our life from personable healthcare mobile waerable devices to all connected and fully integrated smart home and office areas (connected everywhere). This tutorial gives a very good solid intro for the art of digital ASICS targetting IoT devices. A comprehensive coverage of ultra-low-power design methods at the digital ASIC design level will be presented. Lastly, a sample design with tape-out proven EDA tools scripts will be explained and given to attendees to start designing their IoTs immediately.



Learning Objectives:

- IoT Design challenges for Digital ASIC design
- Techniques for realizing ultra low-power IoT designs
- ASIC Design Flow form concept to GDSII
- Basics of Synthesis
- Floorplaning tricks and techniques
- Place and Route and chip finishing
- How to guarantee first time success silicion

Tutorial outline:

• Digital ASIC requirment for IoT
• How to understand a chip design problem and how does that affect the rest of the chip design flow
• System Level design and its importance for contemporary design realization
• How to achive ultra-low power IoT ASIC’s throughout the whole ASIC design flow
• RTL development and design verification
• Concepts of Synthesis, place, route, clock-tree
• Static Timing Analysis & other formal verification methods
• Chip finishing
• Sample design, flow & scripts (based on Synopsys ASIC design tools)

Presenter 1: Dr. Hani Saleh

Hani Saleh is an assistant professor of electronic engineering at Khalifa University since 2012. He is an active member in KSRC (Khalifa University Research Center) where he leads a projects for the development of wearable blood glucose monitor SOC and a mobile surveillance SOC. Hani has a total of 19 years of industrial experience in ASIC chip design, microprocessor design, DSP core design, graphics core design and embedded system design.



Hani experience spans DSP core design, microprocessor peripherals design, microprocessors and graphics core deign. Prior to joining Khalifa University he worked as a Senior Chip Designer (Technical Lead) at Apple incorporation; where he worked on the design and implementation of Apple next generation graphics cores for its mobile products (iPad, iPhone, ...etc.), prior to joining Apple, he worked for several leading semiconductor companies including Intel (ATOM mobile microprocessor design), AMD (Bobcat mobile microprocessor design), Qualcomm (QDSP DSP core design for mobile SOC’s), Synopsys (a key member of Synopsys turnkey design group where he taped out many ASICs and designed the I2C DW IP included in Synopys DesignWare library), Fujitsu (SPARC compatible high performance microprocessor design) and Motorola Australia (M210 low power microprocessor synthesizable core design).



Hani received a Bachelor of Science degree in Electrical Engineering from the University of Jordan, a Master of Science degree in Electrical Engineering from the University of Texas at San Antonio, and a Ph.D. degree in Computer Engineering from the University of Texas at Austin. Hani research interest includes DSP algorithms design, DSP hardware design, computer architecture, computer arithmetic, SOC design, ASIC chip design, FPGA design and automatic computer recognition. Hani has 11 issued US patents, 3 pending patent application, and over 81 articles published in peer review conferences and Journals in the areas of digital system design, computer architecture, DSP and computer arithmetic.



Presenter 2: Prof. Mohammed Ismail

Mohammed Ismail spent over 25 years in academia and industry in the U.S. and Europe. He served as a Faculty Member with the Ohio State University’s (OSU) ElectroScience Laboratory, Columbus, OH, USA.



He was a Research Chair with the Swedish Royal Institute of Technology, Stockholm, Sweden, where he founded the Radio and Mixed Signal Integrated Systems Research Group. He held visiting appointments with Aalto University, Espoo, Finland, the Norwegian Institute of Technology, Trondheim, Norway, the University of Oslo, Oslo, Norway, Twente University, Enschede, The Netherlands, and the Tokyo Institute of Technology, Tokyo, Japan.



He joined the Khalifa University of Science, Technology and Research, Abu Dhabi, United Arab Emirates, in 2011, where he holds the ATIC Professor Chair and is the Head of the Electrical and Computer Engineering Department, which exists on both campuses in Sharjah and Abu Dhabi. He advised the work of over 50 Ph.D. degree students and over 100 M.S. degree students. He has served as a Corporate Consultant to over 30 companies and is the Co-Founder of Micrys Inc., Columbus, Spirea AB, Stockholm, Firstpass Technologies Inc., Dublin, OH, USA, and ANACAD (currently part of Mentor Graphics), Cairo, Egypt.



He is currently a prolific author and an entrepreneur in chip design and test. He is the Founder of the OSU’s Analog VLSI Laboratory, one of the foremost research entities in the field of analog, mixed signal, and RF integrated circuits. He serves as the Director of KSRC and the Co-Director of the ATIC-SRC Center of Excellence on Energy Efficient Electronic Systems targeting self-powered chip sets for wireless sensing and monitoring, biochips, and power management solutions. He has authored or co-authored over 20 books and over 150 journal publications and holds eight U.S. patents issued and several pending. His current research interests include self-healing design techniques for CMOS RF and millimeter wave ICs in deep nanometer nodes.



Prof. Ismail received the U.S. Presidential Young Investigator Award, the Ohio State Lumley Research Award four times in 1992, 1997, 2002, and 2007, and the U.S. Semiconductor Research Corporations Inventor Recognition Award twice. He is the Founding Editor of the Journal of Analog Integrated Circuits and Signal Processing (Springer) and serves as the Journals Editor-in-Chief. He has served the IEEE in many editorial and administrative capacities. He is the Founder of the IEEE International Conference on Electronics, Circuits and Systems and the Flagship Region 8 Conference of the IEEE Circuits and Systems Society.



Joint Publications by the two presenters:

1. N. Bayasi, T. Tekeste, H. Saleh, B. Mohammad, A. Khandoker and M. Ismail, "Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 5, pp. 1962-1974, May 2016. doi: 10.1109/TVLSI.2015.2475119 Won the IEEE Very Large Scale Integration Systems Best Journal Paper award in 2016.
2. Mohammad, B.S.; Saleh, H.; Ismail, M., "Design Methodologies for Yield Enhancement and Power Efficiency in SRAM-Based SoCs," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.PP, no.99, pp.1,1, Oct. 2014. doi: 10.1109/TVLSI.2014.2360319
3. Wahbah, M.; Alhawari, M.; Mohammad, B.; Saleh, H.; Ismail, M., "Characterization of Human Body-Based Thermal and Vibration Energy Harvesting for Wearable Devices," Emerging and Selected Topics in Circuits and Systems, IEEE Journal on , vol.4, no.3, pp.354,363, Sept. 2014. doi: 10.1109/JETCAS.2014.2337195 doi: 10.1109/TVLSI.2015.2440392
4. M. Alhawari; B. Mohammad; H. Saleh; M. Elnaggar, "An Efficient Zero Current Switching Control for L-based DC-DC Converters in TEG Applications," in IEEE Transactions on Circuits and Systems II: Express Briefs , vol.PP, no.99, pp.1-1 doi: 10.1109/TCSII.2016.2558110
5. Maisam Wahbah, Mohammad Alhawari, Baker Mohammad, Hani Saleh, Mohammed Ismail, “An AC–DC converter for human body-based vibration energy harvesting,” Elsevier Microelectronics Journal, July, 2016. doi: http://dx.doi.org/10.1016/j.mejo.2016.06.006
6. D. Kilani; M. Alhawari; B. Mohammad; H. Saleh; M. Ismail, "An Efficient Switched-Capacitor DC-DC Buck Converter for Self-Powered Wearable Electronics," in IEEE Transactions on Circuits and Systems I: Regular Papers , vol.PP, no.99, pp.1-10 doi: 10.1109/TCSI.2016.2586117
7. Mohammad Khader , Agaian Sos and Saleh Hani, "Arabic License Plate Recognition System,"Columbia International Publishing, Dec 2012, doi: 0.7726/jspta.2013.1002.
8. Mohammad Alhawari, Baker Mohammad, Hani Saleh, and Mohammed Ismail, “An Efficient Polarity Detection Technique for Thermoelectric Harvester in L-based Converters,” in IEEE Transactions on Circuits and Systems I. doi: 10.1109/TCSI.2016.2619758.
9. T. Tekeste, N. Bayasi, H. Saleh, A. Khandoker, B. Mohammad and M. Ismail, “A Nano-Watt ECG Feature Extraction Engine in 65nm Technology,” IEEE Transactions on Circuits and Systems II.
10. M. Yasin; T. Tekeste; H. Saleh; B. Mohammad; O. Sinanoglu; M. Ismail, "Ultra-Low Power, Secure IoT Platform for Predicting Cardiovascular Diseases," in IEEE Transactions on Circuits and Systems I: Regular Papers , vol.PP, no.99, pp.1-14 doi: 10.1109/TCSI.2017.2694968

TUTORIAL 2

Neural networks for circuit and signal analysis and synthesis

Presenter: Prof. Mounir Boukadoum

Professor Boukadoum canceled his tutorial lecture due to "Two trips combined would amount to 8 days on planes and airport layovers near the end of a school semester. This forces me to cancel my participation in ICECS 2017 and I apologize for the inconvenience."



​We also apologize for this inconvenience and announce that any fees paid to attend this tutorial will be refunded.


TUTORIAL 3

Design of Broadband Matching Networks and RF and Microwave Amplifiers Using Real Frequency Synthesis Robots

Abstract

Broadband matching networks, RF and microwave amplifiers are the vital building blocks of many wireless communications systems. Expected investments for new generation base stations will be about $500 Billion within next 3 years. As of today, total number of connected devices is more than 50 Billion units, which covers several hundreds of billions dollars of systems. Many kinds of radar investments for various applications (Land Radars, Mobile radars, Smart Cars, surveillance) will amount to trillions of dollars up to 2025. Hence, emerging global wireless market demands the design and mass production of many varieties of broadband matching networks, low-noise small signal and high power microwave amplifiers utilizing devices over several hundreds of MHz to X-Band. Especially, power transistors shows weird input and output load-pulled measured input and output impedances. As the operating frequency increases, real parts of the impedances drastically drops from several tenth ohms down to fractions of ohms. That is to say away from 50 ohms requiring more than 1 to 100 impedance transformation ratio. Therefore, design of Input and output matching networks (IMN & OMN) for the wideband amplifiers become highly crucial. Furthermore, element values of IMN and OMN shows wide spread which may be difficult to manufacture if not impossible. In this case, design philosophy and methods of matching networks become very important to end up with reasonable gain, high Power Added Efficiency over wide frequency band of operations.



One have the following options to design IMN and OMNs
• Design with Lumped Circuit Elements
• Design with Commensurate Transmission lines (or equivalently distributed elements) implemented as microstrips lines, coplanar lines etc.
• Design with mixed lumped and distributed elements (in short, with mixed elements).



In the current literature [1-3], it is shown that, the Real Frequency Techniques (RFTs) provides excellent solutions to matching and amplifier design problems yielding optimum circuit topologies.



Therefore, this tutorial is devoted to RFTs to construct broadband matching networks and wideband amplifiers.



Tutorial consist of two parts. In the first part, we will review the basic design principals and physical limitations to construct broadband matching networks and wideband amplifiers. Then, Real Frequency Techniques (RFTs) are summarized. In this regard, Real Frequency-Line segments technique (RF-LT), Real Frequency-Direct Computational Technique (RF-DCT), Real-Frequency-Parametric Approach (RF-PA) and Simplified Real Frequency Technique (SRFT) is covered.



Several actual matching networks and amplifier design examples are presented. It is worth mentioning that design examples are constructed employing lumped, distributed and mixed circuit elements.

Darlington synthesis is the crucial part and the last step of RFTs. Therefore, in the second part of the tutorial, we introduce our high precision network synthesis tools or robots, which yield optimum matching topologies with element values.



The tutorial material is based on our papers and books published on RFTs. The major books are given as follows.



[1] A. Grobennikov, N. Kumar and B.S. Yarman, Broadband RF and Microwave Amplifiers, CRS Press of Taylor and Francis, 2016.
[2] B.S. Yarman, Design of Ultra Wideband Power Transfer Networks, Wiley Communication Series 2010.
[3] B.S. Yarman, Design of Ultra Wideband Antenna Matching Networks, Springer 2008.

Tutorial Schedule: December 5, 2017, Hilton Batumi, Georgia
Part I: 09.30-12.00 (Morning Session)
Lunch Break: 12.00-14.00
Part II: 14.00-16.30 (Afternoon Session)

Presenter: Prof. Binboga Siddik Yarman

Binboga Siddik Yarman received his BSc Degree from Technical University of Istanbul in Feb. 1974; MSc. Degree from Stevens Institute of Technology (June 1977), Hoboken, N.J., USA, and Ph.D. Degree from Cornell University (January 1982), Ithaca, NY, USA.



He was a Member of Technical Staff at General David Sarnoff Microwave Technology and Research Center, in Princeton, NJ, USA.



He served as professor and administrator at various Universities:
Anadolu University, Middle East Technical University, Istanbul University, Isik University of Turkey; Technical University of Istanbul, Ruhr University of Germany, Tokyo Institute of Technology of Japan, Wuhan Technology University of China.



He is one of the founders of Savronik Group of Companies and recently serves as the Chairman of the Board of Dirctors.



He was the founding president of Isik University (1996-2004) and used to served as the Chairman of Board of Trustees (2009-2016).



He published numerous papers in the field of Microwave Engineering, Circuit and Systems, Signal Processing, Mathematical Modeling and Decision Making.



He has published 4 books: Design of Ultra - Wideband Antenna Matching Networks by Springer (2008), Design of Ultra - Wideband Power Transfer Networks by Wiley (2010), Intelligence Based Decision Making by Nobel Press of Turkey (2014) and He is one of the co-author of the book titled “Broadband Microwave and RF Power Amplifiers” by CRC (November 2015).



He holds 4 US and 9 Turkish Patents.



He was the recipient of Young Turkish Scientist Award (1986), Technology Award (1987) of Scientific and Research Council of Turkey. He is a member of New York Academy of Science (1994), selected as the Man of the year in Science and Technology of Cambridge Biography (1999). He is a Fellow of IEEE; Alexander Von Humboldt Fellow and Salzburg Fellow of USIS.




Breaking news

Dear Delegates,
Conference Venue Hilton Batumi Hotel rooms now available at same discounted rate until 13th of November 2017, Monday 16:00 hrs. Turkish Time.
Therefore, please complete your Hotel reservations from registration web site before announced time.
Rooms will be booked only upon availability and at a different rate after this time.

Conference program is now available.

Click here to proceed to the program.

Registration is now open. NEWEST

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Important Dates NEWER

July 25, 2017
Special Session and Tutorials Proposals

August 1, 2017
Notification of Special Session Acceptance

September 5, 2017
Paper Submissions

October 15, 2017
Notification of Paper Acceptance

October 31, 2017
Camera-Ready Paper Submission

NEW

Extended versions of selected ICECS 2017 papers will be invited to submit to a special issue of TCAS 1.

Contact

For inquiries, please e-mail to icecs2017@isikun.edu.tr.